Semiconductor storage device and method of manufacturing the same

ABSTRACT

According to one embodiment, coupling capacitance in a state in which a first heat radiation member is arranged between parallel flat plates of a first capacitor formed by a surface of a housing opposed to one surface of a printed circuit board and the printed circuit board is smaller than coupling capacitance in a state in which an integrally formed object having a relative dielectric constant of 5.8 is arranged between the first capacitor to cover a first radiating region containing the controller and the first nonvolatile semiconductor memories.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. application Ser. No. 13/010,475, filedJan. 20, 2011, which is a continuation-in-part of application Ser. No.12/839,785, filed Jul. 20, 2010, now abandoned, and is based upon andclaims the benefit of priority from the prior Japanese PatentApplications No. 2009-172942, filed on Jul. 24, 2009, Japanese PatentApplication No. 2009-293492, filed on Dec. 24, 2009, and Japanese PatentApplication No. 2010-121629, filed on May 27, 2010, the entire contentsof all of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storagedevice and a method of manufacturing the same.

BACKGROUND

As an auxiliary storage device mounted on a computer, an auxiliarystorage device including a hard disk drive (HDD) (hereinafter, “HDDdevice”) is used (see Japanese Patent Application Laid-Open NO.2004-30837).

In recent years, an auxiliary storage device including, as a recordingmedium, a nonvolatile semiconductor memory such as a NAND flash memory(so-called solid state disk, hereinafter, “SSD device”) is mounted on acomputer instead of the HDD device. In the SSD device, a plurality ofNAND flash memories (hereinafter, “NANDs”) and a controller integratedcircuit (IC) that controls the NANDs are mounted on a printed circuitboard via electrodes (bumps). The SSD device is mounted on the computerafter being housed in a housing generally having an external dimensionand a shape same as those of the HDD device specified by a standard(e.g., a housing having a size and a shape same as those of a 2.5-inchHDD device). There are several kinds of standards concerning the housingof the HDD device according to the sizes of magnetic disks. In general,a housing such as that for the 2.5-inch HDD device is a box made ofmetal.

When the SSD device actually operates (when data is actually read andwritten), a controller generates heat because switching operation isrepeatedly performed at high speed. A part of the heat generated fromthe controller is transmitted to the printed circuit board via the bumpset in contact with the controller and further transmitted to the NANDsvia a wiring pattern on the printed circuit board the bumps set incontact with the NANDs. In an operation principle, under ahigh-temperature environment, the NANDs tend to unsteady operate becauseleak current increases. Therefore, operation guarantee temperature forthe NANDs is set low compared with other kinds of ICs. For example,whereas the operation guarantee temperature of the NANDs is about 85°C., the operation guarantee temperature of the other kinds of ICs isabout 100° C.

Therefore, in the SSD device, it is necessary to cool the controller tosuppress the transmission of the heat from the controller to the NANDs.In the case of the HDD device including a magnetic disk as a recordingmedium, because the controller and the magnetic disk are arrangedseparately from each other, the heat generated from the controller doesnot affect a mechanical section and the like of the magnetic disk.Therefore, it can be said that this problem is peculiar to the SSDdevice.

As a structure for cooling the controller in the SSD device, it isconceivable to interpose a heat radiation sheet between the controllerand a bottom housing. Even if the heat radiation sheet is interposedbetween the controller and the bottom housing, the entire heat generatedfrom the controller is not always transmitted to the bottom housing.However, a part of the heat is transmitted to the bottom housing via theheat radiation sheet. Consequently, a heat quantity transmitted to theNANDs is reduced to maintain the temperature of the NAND not to exceedthe operation guarantee temperature.

According to the improvement of the performance of the SSD device andthe computer mounted with the SSD, a heat value during actual operationof the controller tends to increase. For example, a data transfer rateof the SSD in the past is 100 MByte/sec for readout and 40 MByte/sec forwriting. Currently, the data transfer rate is improved to 240 MByte/secfor readout and 200 MByte/sec for writing. Therefore, even if the heatradiation sheet is arranged between the controller and the bottomhousing, it is difficult to sufficiently radiate the heat generated fromthe controller. However, an SSD device that takes measures against thisproblem is not realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram of the configuration of an SSD device and theconfiguration of a lower surface of a printed circuit board according toa first embodiment;

FIG. 1B is a diagram of the configuration on the lower surface side ofthe printed circuit board of the SSD device according to the firstembodiment;

FIG. 2 is a plan view of the internal structure of the SSD deviceaccording to the first embodiment;

FIG. 3A is a partially enlarged perspective view of an interferencesection of the printed circuit board in a state in which a screw is notinserted into a screw hole;

FIG. 3B is a partially enlarged perspective view of the interferencesection of the printed circuit board in a state in which the screw isinserted into the screw hole from a side;

FIG. 4 is a partially enlarged plan view of the periphery of theinterference section in a circuit pattern;

FIG. 5A is an arrow sectional view taken along line VA, VB-VA, VB shownin FIG. 4 of a printed circuit board used in a module-type semiconductorstorage device;

FIG. 5B is an arrow sectional view taken along line VA, VB-VA, VB shownin FIG. 4 of a printed circuit board used in a box-type semiconductorstorage device;

FIG. 6 is a plan view of a sheet-like substrate;

FIG. 7 is a block diagram of the schematic configuration of a PC boardprocessing apparatus;

FIG. 8 is a flowchart for explaining a PC board processing process;

FIG. 9 is a diagram of the configuration of a template includingthrough-holes in places corresponding to a controller and NANDs;

FIG. 10 is a diagram of a state in which a gel member of a roomtemperature curing type before curing is injected into a predeterminedposition in a bottom housing;

FIG. 11 is diagram of a state after completion of assembly of an SSDapparatus including a semiconductor memory device;

FIG. 12 is a diagram of the configuration of an SSD device using aradiation sheet integrally formed to cover a radiating region containingthe controller and NANDs;

FIG. 13 is a diagram of a model of a parallel flat capacitor formed by aprinted circuit board and a bottom housing;

FIG. 14 is a graph of an EMI characteristic of an SSD device includingindividual heat radiation sheets;

FIG. 15 is a graph of an EMI characteristics of an SSD device using aradiation sheet integrally formed to cover the radiating regioncontaining the controller and NANDs;

FIG. 16 is a diagram of an example in which one heat radiation sheet isarranged for each of a plurality of cooling targets;

FIG. 17 is a diagram of the configuration of an SSD device according toa second embodiment;

FIG. 18 is a perspective view of heat radiation sheets according to athird embodiment;

FIG. 19 is a diagram of the configuration of an SSD device including aprinted circuit board mounted with NANDs on both sides thereof and theconfiguration of a lower surface of the printed circuit board mountedwith the NANDs on both the sides;

FIGS. 20A and 20B are diagrams illustrating the printed circuit board ofthe SSD device according to a fourth embodiment;

FIG. 21A is a diagram illustrating temperature measurement results whena SSD device according to the fourth embodiment is caused tocontinuously write data at the transfer rate of 192 MB/sec;

FIG. 21B is a diagram illustrating temperature measurement locations oneach component mounted on a printed circuit board; and

FIG. 22 is a diagram illustrating temperature differences between eachdevice mounted on the printed circuit board and the housing and maximumtemperatures of devices when the housing temperature is assumed to be70° C.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor storage deviceincludes: a printed circuit board mounted on with, one surface,respectively via a plurality of bumps, a plurality of first nonvolatilesemiconductor memories and a controller that controls reading of datafrom and writing of data in the first nonvolatile semiconductormemories; a housing that is formed of a conductive material and housesthe printed circuit board; and a first heat radiation member that isinterposed between a surface of the housing opposed to one surface ofthe printed circuit board and the controller and first nonvolatilesemiconductor memories and thermally connects the controller and firstnonvolatile semiconductor memories and the housing. The couplingcapacitance in a state in which the first radiation member is arrangedbetween a first capacitor formed by the surface of the housing opposedto one surface of the printed circuit board and the printed circuitboard is smaller than coupling capacitance in a state in which anintegrally formed object having a relative dielectric constant of 5.8 isarranged between the first capacitor to cover a first radiating regioncontaining the controller and the first nonvolatile semiconductormemories.

Exemplary embodiments of semiconductor storage device and method ofmanufacturing the same will be explained below in detail with referenceto the accompanying drawings. The present invention is not limited tothe following embodiments.

First embodiment

FIG. 1A is a disassembled perspective view of the configuration of anSSD device according to a first embodiment. FIG. 1B is a perspectiveview of the configuration on a lower surface side of a printed circuitboard 3. FIG. 2 is a plan view of the internal structure of the SSDdevice according to the first embodiment. The SSD device according tothis embodiment includes the printed circuit board 3 mounted with, onthe lower surface side, eight NANDs 5 as first nonvolatile semiconductormemories and a controller 6. The printed circuit board 3 is housed in ahousing formed by a top cover 1 and a bottom housing 9. The top cover 1and the bottom housing 9 are formed of a metal material such as aluminumor iron.

The top cover 1 and the bottom housing 9 are coupled by cover fixingscrews 2 to form a housing having a substantial hexahedron shape openedon one side. The printed circuit board 3 is screwed to the bottomhousing 9 by fixing screws 8 in a state in which heat radiation sheets10 (first heat radiation members) are interposed between the controller6 and NANDs 5 and the bottom housing 9. A connector 4 is arranged at oneend of the printed circuit board 3. The connector 4 is an interface thatconnects a host apparatus such as a computer and the SSD device. A shapeand the like of the connector 4 are decided to conform to, for example,a serial advanced technology attachment (SATA) standard as a connectioninterface standard. The connector 4 is exposed to the outside of thehousing in an opened surface of the housing. The SSD device is connectedto the computer as the host apparatus that is an apparatus on which theSSD is mounted. In the following explanation, the printed circuit board3 mounted with the connector 4, the NANDs 5, and the controller 6 isalso referred to as semiconductor memory device 50. The SSD deviceaccording to this embodiment is a box-type semiconductor storage devicein which the semiconductor memory device 50 is housed in a housing of a2.5-inch type same as the housing of the HDD device.

Each of the heat radiation sheets 10 is formed to have flexibility witha material containing silicone resin and ceramics filler. Each of theheat radiation sheets 10 is pressed by the controller 6, the NAND 5, andthe bottom housing 9 mounted on the printed circuit board 3 and closelyattached to both of the printed circuit board 3 and the controller 6,the NAND 5, and the bottom housing 9. Consequently, the controller 6,the NAND 5, and the bottom housing 9 are thermally connected. An SDRAM 7has high heat resistance. No deficiency occurs even if heat from thecontroller 6 is transited to the SDRAM 7. Therefore, the heat radiationsheet 10 is not arranged between the SDRAM 7 and the bottom housing 9.The heat radiation sheet 10 has a size for realizing a heat radiationeffect sufficient for preventing the temperature of the controller 6 andthe NAND 5 from rising to be equal to or higher than a design value(e.g., 85° C. as the operation guarantee temperature). As explainedlater, the first heat radiation member is not limited to a heatradiation sheet molded in a sheet shape and can be a gel member.However, in an example explained below, the heat radiation sheet isused.

The printed circuit board 3 has a multilayer structure formed bysuperimposing synthetic resin. In this embodiment, the printed circuitboard 3 has an eight-layer structure. On the printed circuit board 3, acircuit pattern 3 a (not shown in FIG. 1A) is formed in various shapeson the surfaces or the insides of the layers formed of the syntheticresin. The NANDs 5, the controller 6, and the connector 4 mounted on theprinted circuit board 3 are electrically connected via the circuitpattern 3 a formed on the printed circuit board 3.

In the SSD device according to this embodiment as the box-typesemiconductor storage device, in the semiconductor memory device 50, asshown in FIG. 2, a center axis AX thereof is arranged to be shifted withrespect to a center axis BX of the bottom housing 9. This is because theposition of the connector 4 with respect to the housing is decided by astandard such as serial ATA revision 2.6. Because the center axis AX andthe center axis BX are shifted from each other, one side of the printedcircuit board 3 is set close to a wall surface of the housing.

FIG. 3A is a partially enlarged perspective view of an interferencesection 3 b of the printed circuit board 3 in a state in which a screw24 is not inserted into a screw hole 9 a. FIG. 3B is a partiallyenlarged perspective view of the interference section 3 b of the printedcircuit board 3 in a state in which the screw 24 is inserted into thehole 9 a from a side. When the SSD device is fixed to the host apparatussuch as the computer, the fixing screw 24 (housing fixing means) isinserted from the side or the bottom of the bottom housing 9. To insertthe screw 24, screw holes 9 a are respectively formed on the side andthe bottom.

The screw 24 inserted into the screw hole 9 a on a direction side towhich the center axis AX of the semiconductor memory device 50 isshifted interferes with a part (the interference section 3 b) of theprinted circuit board 3 set close to the wall surface of the housing.

In the printed circuit board 3 used in the SSD device according to thisembodiment, the interference section 3 b is cut out to form a cutout 3c. Therefore, the screw 24 and the printed circuit board 3 can beactually prevented from interfering with each other. Therefore, theprinted circuit board 3 can be prevented from being broken or bent byinterference with the screw 24. Specifically, the cutout 3 c is formednear the connector 4 and on one side of the printed circuit board 3 thatis close to the wall surface of the housing when the semiconductormemory device 50 is housed in the housing.

The printed circuit board 3 can also be used in a module-typesemiconductor storage device in which the semiconductor memory device 50is used without being housed in a housing or the like to conform to theMO-297 standard set up by the Joint Electron Device Engineering Council(JEDEC).

In the semiconductor memory device 50 for the module-type semiconductordevice and the semiconductor memory device 50 for the box-typesemiconductor storage device, a part of a shape of the printed circuitboard 3 included in the semiconductor memory device 50 is different.Specifically, a part of the printed circuit board 3 of the semiconductormemory device 50 for the box-type semiconductor storage device is cutout to form the cutout 3 c.

An external dimension and the like of the module-type semiconductorstorage device are specified by, for example, the MO-297 standard of theJEDEC. In the module-type semiconductor storage device, because thesemiconductor memory device 50 is used without being housed in thehousing, an external dimension and the like of the semiconductor memorydevice 50 itself are specified. Consequently, an external dimension andthe like of the printed circuit board 3 included in the semiconductormemory device 50 are also specified.

FIG. 4 is a partial enlarged plan view of the periphery of theinterference section 3 b. The MO-297 standard of the JEDEC specifiesthat, as shown in FIG. 4, a hole 3 d is provided in a section equivalentto the cutout 3 c. Therefore, it is difficult to form the cutout 3 c inthe printed circuit board 3 in the module-type semiconductor storagedevice. However, when the SSD device is used as the module-typesemiconductor storage device, because the semiconductor memory device 50is not housed in the housing, interference with a screw does not pose aproblem even when the cutout 3 c is not formed. The hole 3 d provided inthe section equivalent to the cutout 3 c is used, for example, when theSSD device as the module-type semiconductor storage device is fixed tothe host apparatus such as the computer by using a screw. A hole 3 eformed near the hole 3 d is used when the semiconductor memory device 50as the box-type semiconductor storage device is fixed to the housing(the bottom housing 9).

As explained above, the printed circuit board 3 is also used when theSSD device is configured as the module-type semiconductor storagedevice. Therefore, a discriminating section 14 is formed as shown inFIG. 2. The discriminating section 14 is formed to discriminate whetherthe printed circuit board 13 is used in the module-type semiconductorstorage device or used in the box-type semiconductor storage device.Information necessary for manufacturing such as lot numbers ofcomponents mounted on the printed circuit board 3 can also be managed byusing the discriminating section 14. The discriminating section 14 is,for example, a two-dimensional code printed to be readable from thesurface of the printed circuit board 3. The discriminating section 14 isprinted by a marker or the like before the NANDs 5 and the like aremounted. The discriminating section 14 is formed to avoid positionswhere the NANDs 5 and the like are mounted. Therefore, thediscriminating section 14 is readable even after the NANDs 5 and thelike are mounted. The discriminating section 14 only has to be able todiscriminate whether the semiconductor memory device 50 is used as themodule-type semiconductor memory or used as the box-type semiconductorstorage device. The discriminating section 14 is not limited to thetwo-dimensional code. For example, the discriminating section 14 can bea barcode or can be an IC chip. The discriminating section 14 can be adifference of a shape such as unevenness formed on the printed circuitboard 3. The discriminating section 14 can be formed in a place otherthan a position shown in the figure. For example, the discriminatingsection 14 can be printed on the surface of each of devices such as theNANDs 5.

The configuration of the circuit pattern 3 a formed on the printedcircuit board 3 is explained below. FIG. 5A is an arrow sectional viewtaken along line VA, VB-VA, VB shown in FIG. 4 of the printed circuitboard 3 used in the module-type semiconductor storage device. FIG. 5B isan arrow sectional view taken along line VA, VB-VA, VB shown in FIG. 4of the printed circuit board 3 used in the box-type semiconductorstorage device. A conductive metal material, for example, copper is usedfor the circuit pattern 3 a. The circuit pattern 3 a is formed insubstantially the entire region in plan view of the printed circuitboard 3. However, as shown in FIG. 4, the circuit pattern 3 a is formedto avoid the interference section 3 b. A space (a resin region where thecircuit pattern 3 a is not formed) Y is provided between a cut line incutting out the interference section 3 b (a formation line of the cutout3 c) and the circuit pattern 3 a. In this embodiment, Y is set to 0.5millimeter. In the semiconductor memory device 50, in some case, a screwinserted into the hole 3 d provided in the section equivalent to thecutout 3 c and the circuit pattern 3 a are set in contact with eachother and grounded. By suppressing the space Y to a predetermineddistance, the head of the screw and the circuit pattern 3 a can be setin contact with each other and grounded.

The circuit pattern 3 a is formed in other layers different from thelayer shown in FIG. 4. Only an example of the circuit pattern 3 a isshown in FIG. 4. In all the layers different from the layer shown inFIG. 4, the circuit pattern 3 a is formed to avoid the interferencesection 3 b and the space Y is provided. The devices such as the NANDs 5are not arranged in the interference section 3 b.

As shown in FIG. 5B, because the predetermined space Y is providedbetween the cut line in cutting out the interference section 3 b and thecircuit pattern 3 a, the circuit pattern 3 a is not exposed at an edge 3f when the interference section 3 b is cut out.

FIG. 6 is a plan view of a sheet-like substrate 19. The sheet-likesubstrate 19 includes printed circuit boards 3 and a peripheral section16. The peripheral section 16 is provided to surround the printedcircuit boards 3 and coupled to the printed circuit boards 3 viacoupling sections 18. The peripheral section 16 surrounds the printedcircuit boards 3 having unevenness in an external shape thereof andforms an external shape of the sheet-like substrate 19 in asubstantially square shape. Consequently, handleability of the printedcircuit boards 3 in mounting the NANDs 5 is improved.

The NANDs 5 and controllers 6 are mounted on the sections of the printedcircuit boards 3 in a state of the sheet-like substrate 19 to which theperipheral section 16 is coupled. The peripheral section 16 can beseparated to obtain the semiconductor memory device 50 from thesheet-like substrate 19 by cutting off the coupling sections 18 using adrill of a divider. Cutouts 3 c of the printed circuit boards 3 areformed when the coupling sections 18 are cut off. In this embodiment,four semiconductor memory devices 50 can be obtained from one sheet-likesubstrate 19 by separating the peripheral section 16 from the sheet-likesubstrate 19 mounted with the NANDs 5 and the controllers 6. The numberof semiconductor memory devices 50 that can be obtained from the onesheet-like substrate 19 is not limited to four. A larger number ofsemiconductor memory devices 50 can be obtained from the one sheet-likesubstrate 19 by using a larger sheet-like substrate 19. Onesemiconductor memory device 50 can be obtained from the one sheet-likesubstrate 19.

FIG. 7 is a block diagram of the schematic configuration of a PC boardprocessing apparatus (manufacturing apparatus). A PC board processingapparatus 30 includes a drill 31, a reading unit 33, and a control unit34. The drill 31 functions as a cutting unit that cuts off the couplingsections 18 of the sheet-like substrate 19 and cuts out the interferencesection 3 b. The reading unit 33 reads the discriminating section 14 anddiscriminates whether the printed circuit board 13 is used in themodule-type semiconductor storage device or used in the box-typesemiconductor storage device. The control unit 34 automatically readsprocessing data and controls the drill 31 based on a discriminationresult of the reading unit 33 to cut off the coupling sections 18 andcut out the interference section 3 b.

FIG. 8 is a flowchart for explaining a PC board processing process.First, devices such as the NANDs 5, the controllers 6, and connectors 4are mounted on the sheet-like substrate 19 (step S1). Subsequently,discriminating sections 14 are read and processing data is automaticallyread based on a discrimination result (step S2). When it isdiscriminated that the printed circuit boards 3 are used in the box-typesemiconductor storage device (“Yes” at step S3), the coupling sections18 are cut off and interference sections 3 b are cutout by the drill 31to form the cutouts 3 c (step S4). Consequently, the four semiconductormemory devices 50 in which the cutouts 3 c are formed are obtained fromthe one sheet-like substrate 19.

When it is discriminated at step S3 that the printed circuit boards 3are not used in the box-type semiconductor storage device but is used inthe module-type semiconductor storage device (“No” at step S3), thecutouts 3 c are not formed and the coupling sections 18 are cut off(step S5). Consequently, the four semiconductor memory devices 50 inwhich the cutouts 3 c are not formed are obtained from the onesheet-like substrate 19. The step of forming the cutouts 3 c and thestep of cutting off the coupling sections 18 can be separately performedand whichever of the steps can be performed earlier.

As explained above, the circuit pattern 3 a is formed to avoid theinterference section 3 b of the printed circuit board 3 and the devicessuch as the NANDs 5 are arranged to avoid the interference section 3 b.Therefore, the arrangement of the circuit pattern 3 a and the devices ofthe printed circuit board 3 can be used in common irrespectively ofwhether the semiconductor memory device 50 is used in the module-typesemiconductor storage device or used in the box-type semiconductorstorage device. The arrangement of the circuit pattern 3 a and thedevices of the printed circuit board 3 can be used in commonirrespectively of presence or absence of the cutout 3 c. This makes itpossible to suppress design cost for the arrangement of the circuitpattern 3 a and the devices. Because mounting evaluation and performanceevaluation can be used in common, it is also possible to suppressevaluation cost. Because the devices to be mounted can be used incommon, it is also possible to suppress selection cost for the devices.When the semiconductor memory device 50 is used in the module-typesemiconductor storage device, because the cutout 3 c is not formed, itis possible to satisfy the formation of a hole requested by the MO-297standard. On the other hand, when the semiconductor memory device 50 isused in the box-type semiconductor storage device, it is possible toprevent interference between the screw and the printed circuit board 3by forming the cutout 3 c.

Because the circuit pattern 3 a is formed to avoid the interferencesection 3 b, when the cutout 3 c is formed, the drill 31 does not haveto be caused to cut off the circuit pattern 3 a. Consequently, when thecutout 3 c is formed, it is possible to cause the drill 31 to cut offonly resin. Therefore, the life of the drill 31 can be extended. Asshown in FIG. 5B, the circuit pattern 3 a is not exposed in the edgewhen the interference section 3 b is cut out. Therefore, a metal burrless easily occurs at the edge. This makes it possible to prevent themetal burr from short-circuiting the circuit patterns 3 a formed amongthe layers of the printed circuit board 3. It is also possible toprevent the metal burr from separating from the printed circuit board 3to cause short-circuit and the like in other places.

In the above explanation, when the peripheral section is separated fromthe sheet-like substrate 19, the interference section 3 b is cut out toform the cutout 3 c. However, the formation of the cutout 3 c is notlimited to this. For example, it is also possible to store thesemiconductor memory device 50 as the module-type semiconductor storagedevice without forming the cutout 3 c when the peripheral section isseparated and, when the semiconductor memory device 50 is used in thebox-type semiconductor storage device a posteriori, cut out theinterference section 3 b to form the cutout 3 c.

A procedure for assembling the SSD device including the semiconductormemory device 50 is explained below. First, as shown in FIG. 9, atemplate 20 including through-holes 20 a in places corresponding to thecontroller 6 and the NANDs 5 is arranged in a predetermined position inthe bottom housing 9. The heat radiation sheets 10 are stuck to theinner surface of the bottom housing 9 via the through holes 20 a. Afterthe heat radiation sheets 10 are stuck, the template 20 is removed fromthe bottom housing 9. The semiconductor memory device 50 is mounted onthe template 20 and screwed to the template 20 by the fixing screws 8.(In the figure, a procedure for sticking heat radiation sheets using atemplate is shown. However, the heat radiation sheets can be directlystuck to a package of a corresponding IC without using the template.However, in that case, it is necessary to contrive means for preventingmounted components other than the IC from being damaged during stickingwork.) The heat radiation sheets 10 are respectively interposed betweenthe controller 6 and NANDs 5 and the bottom housing 9 through such aprocedure, whereby setting workability for the heat radiation sheets 10is improved. Because the printed circuit board 3 is assembled to coverthe heat radiation sheets 10, the heat radiation sheets 10 do not fallfrom top surfaces (surfaces opposed to the bottom housing 9) of thecontroller 6 and the NANDs 5 during assembly work. Thereafter, the topcover 1 is placed over the bottom housing 9 and the cover fixing screws2 are tightened, whereby the assembly of the SSD device is completed.

An assembling procedure for an SSD apparatus substituting a gel memberfor the heat radiation sheet as the first heat radiation member isexplained below. First, as shown in FIG. 10, a gel member 22 of a roomtemperature curing type in a state of a fluid is injected into apredetermined position in the bottom housing 9. When the gel member 22is injected, an application amount of the gel member 22 is controlled bya dispenser 23 or the like. Subsequently, the gel member 22 is leftintact in a room temperature state and cured (set). Thereafter, thesemiconductor device 50 is fixed to the bottom housing 9. The NAND 5 andthe controller 6 are brought into contact with the gel member 22.Thereafter, the top cover 1 and the bottom housing 9 are laid one on topof the other and fastened by fixing screws. Consequently, as shown inFIG. 11, the assembly of the SSD apparatus is completed as shown in FIG.11.

In this case, at a point when the semiconductor memory device 50 ishoused in the bottom housing 9, a leak of the gel member 22 already lesseasily occurs. Extrusion and a leak of the gel member 22 do not easilyoccur. Therefore, it is easy to automate an injection process for thegel member 22 using an industrial robot or the like. It is possible torealize a reduction in manufacturing cost.

If the gel member 22 has viscosity and surface tension enough for notspreading exceeding a predetermined area (e.g., an area opposed to theNAND 5 and the controller 6) from application to curing of the gelmember 22, it is also possible to house the semiconductor memory device50 in the bottom housing 9 before the curing of the gel member 22. Inother words, even if the gel member 22 is compressed by the NAND 5, thecontroller 6, and the bottom housing 9 when the semiconductor memorydevice 50 is housed in the bottom housing 9, an application amount ofthe gel member 22 only has to be controlled to an amount enough formaintaining a shape of the gel member 22 with the surface tension andthe viscosity. When a certain length of time elapses after thesemiconductor memory device 50 is housed in the bottom housing 9, thegel member 22 is cured. Therefore, even when the SSD apparatus is usedas a product, it is possible to suppress a leak of the gel member 22.

In general, the gel member is more inexpensive than the heat radiationsheet. Therefore, if the gel member is used, it is possible to realize afurther reduction in manufacturing cost for the SSD apparatus.

A reason for individualizing the heat radiation sheets 10 in thisembodiment is explained below.

As measures against heat of the NANDs, it is conceivable to thermallyconnect the NANDs and the bottom housing via the heat radiation sheets.As an example of this structure, there is a structure in which a heatradiation sheet 11 having a minimum rectangular shape that covers aradiating region (first radiating region) containing a plurality of theNANDs 5 and the controller 6 is interposed between the controller 6 andNANDs 5 and the bottom housing 9. FIG. 12 is a disassembled perspectiveview of an SSD device having a configuration for covering the regioncontaining the controller 6 and the NANDs 5 with one integrally formedheat radiation sheet 11. The SSD device is the same as the SSD deviceshown in FIG. 1A except that the heat radiation sheet 11 has the minimumrectangular shape for covering the controller 6 and the NANDs 5. Theconfiguration of the lower surface of the printed circuit board 3 of thesemiconductor memory device 50 is the same as that shown in FIG. 1B. TheSSD device shown in FIG. 12 is explained below in comparison with theSSD device according to the first embodiment shown in FIG. 1A.

The printed circuit board 3 of the SSD device is arranged substantiallyparallel to the bottom housing 9. Therefore, it can be regarded that aparallel flat capacitor is formed by the printed circuit board 3 and thebottom housing 9. A model of the parallel flat capacitor formed by theprinted circuit board 3 and the bottom housing 9 is shown in FIG. 13.The printed circuit board 3 and the bottom housing 9 are parallel flatplates and coupling capacitance (capacitance) is generated. Because theheat radiation sheets 10 or the heat radiation sheet 11 is arrangedbetween the parallel flat plates, the coupling capacitance fluctuatesaccording to an area of a region where the heat radiation sheets 10 orthe heat radiation sheet 11 is present and a relative dielectricconstant of the heat radiation sheets 10 or the heat radiation sheet 11.

The printed circuit board 3 receives the supply of electric power fromthe computer connected via the connector 4 and operates as an SSD.High-frequency noise occurs from the NANDs 5 and the controller 6because of an internal operation clock and read/write data. The noisepropagates to the bottom housing 9 according to capacitive coupling ofthe printed circuit board 3 and the bottom housing 9.

The bottom housing 9 resonates with respect to an electromagnetic wavehaving a frequency (1/n) times (n=1, 2, 4, 8, . . . ) as high as afrequency with a dimension in a longitudinal, lateral, or diagonaldirection of the bottom housing 9 set as one wavelength and functions asan efficient antenna. For example, if the long side, the short side, andthe diagonal of the bottom housing 9 are 0.1 meter, 0.06985 meter, and0.122 meter, respectively, in the long side direction, electromagneticwaves having frequencies 3 GHz, 1.5 GHz, 0.75 GHz, 0.375 GHz, and thelike resonate. In the short side direction, electromagnetic waves havingfrequencies 4.295 GHz, 2.147 GHz, 1.074 GHz, 0.537 GHz, and the likeresonate. In the diagonal direction, electromagnetic waves havingfrequencies 2.459 GHz, 1.230 GHz, 0.615 GHz, 0.307 GHz, and the likeresonate. The electromagnetic waves having these frequencies areradiated into the air via the bottom housing 9 as an antenna.

In the example explained above, resonant frequencies are present oversubstantially all bands of 300 MHz to 1 GHz included as measurementranges in electromagnetic interference (EMI) standards of countries andregions specified in the CE, the Voluntary Control Council forInterference by information technology equipment (VCCI), the FederalCommunications Commission (FCC), and the like. However, because of adifference in dimensions in the longitudinal, lateral, and diagonaldirections of the bottom housing 9, the resonant frequency of 0.537 GHzat ⅛ wavelength in the short side direction, the resonant frequency of0.615 GHz at ¼ wavelength in the diagonal direction, and the resonantfrequency of 0.750 GHz at ¼ wavelength in the long side direction have asmall frequency difference of a resonant frequency. When operation speedof the SSD device is increased, noise corresponding to the bands tendsto occur and resonate with the bottom housing 9. Therefore, unnecessaryradiation caused by the bottom housing 9 functioning as an antennabecomes more conspicuous according to the increase in the operationspeed of the SSD device.

As explained above, the arrangement of the heat radiation sheets 10 orthe heat radiation sheet 11 to cool the controller 6 and the NANDs 5 isnothing but insertion of an object having a relative dielectric constant(a relative dielectric constant of a material of the heat radiationsheets 10 or the heat radiation sheet 11) between the parallel flatplates of the parallel flat capacitor (between the printed circuit board3 and the bottom housing 9). Therefore, when the heat radiation sheets10 or the heat radiation sheet 11 is arranged, the coupling capacitanceof the parallel flat capacitor increases compared with couplingcapacitance in a state in which the printed circuit board 3 and thebottom housing 9 are simply opposed to each other. The bottom housing 9easily functions as an antenna. When the heat radiation sheet 11integrally formed to cover the radiating region containing thecontroller 6 and the NANDs 5 is set, the coupling capacitance of thecapacitor increases more than the coupling capacitance of the capacitorobtained when the individual heat radiation sheets 10 are arranged.Therefore, the heat radiation sheet 11 integrally formed to cover theradiating region containing the controller 6 and the NANDs 5 isdisadvantageous in terms of a reduction in unnecessary radiation causedby the bottom housing 9 functioning as the antenna.

A relative dielectric constant of a material of an existing heatradiation sheet is about 5.8. When the heat radiation sheet isintegrally formed and arranged to cover the radiating region containingthe controller 6 and the NANDs 5, an EMI characteristic of the SSDdevice can conform to the EMI standard at the very limit. It is likelythat the EMI characteristic does not conform to the standard dependingon shield performance of a computer as an apparatus on which the SSDdevice is mounted. If the operation speed of the SSD device is furtherincreased, it is more highly likely that the EMI characteristic does notconform to the EMI standard. When a margin is given to the EMI standardand stricter specifications are required, it is likely that the requiredspecifications cannot be met even by the current operation speed.

In this embodiment, with the above points taken into account, theindividual heat radiation sheets 10 are adopted to suppress an increasein the coupling capacitance of the parallel flat capacitor. Because theheat radiation sheets 10 are individualized, a total of areas occupiedby the heat radiation sheets 10 is small compared with an area of theheat radiation sheet 11 integrally formed to cover the radiating regioncontaining the controller 6 and the NANDs 5. Therefore, the couplingcapacitance of the capacitor decreases, impedance from a noise source toan antenna side increases, a transmission level decreases, and theunnecessary radiation caused by the bottom housing 9 functioning as theantenna is reduced.

A difference between the use of the individual heat radiation sheets 10and the use of the heat radiation sheet 11 integrally formed to coverthe radiating region containing the controller 6 and the NANDs 5 isexplained more in detail below with reference to specific numericalvalues as examples. However, the present invention is not limited to thenumerical values referred to as the examples.

Each of the individual heat radiation sheets 10 has longitudinal andlateral length of 0.01 meter and thickness of 0.003 meter. The printedcircuit board 3 has longitudinal length of 0.063 meter and laterallength of 0.0865 meter. The bottom housing 9 has a long side of 0.1meter, a short side of 0.06985 meter, and a diagonal of 0.122 meter.

A space between the printed circuit board 3 and the bottom housing 9 is0.0044 meter. Mounting height of the controller 6 and the NANDs 5 is0.0014 meter. Therefore, a space between the controller 6 and NANDs 5and the bottom housing 9 is 0.003 meter.

The heat radiation sheet 11 integrally formed to cover the radiatingregion containing the controller 6 and the NANDs 5 has longitudinallength of 0.05 meter, lateral length of 0.07 meter, and thickness of0.003 meter.

An area of each of the individual heat radiation sheet 10 is 0.0001 m²and an area of the heat radiation sheet 11 integrally formed to coverthe radiating region containing the controller 6 and the NANDs 5 is0.0035 m². Nine individual heat radiation sheets 10 are used in total tocorrespond to the controller 6 and the NANDs 5, respectively. Therefore,an area ratio of a total area S₁ of the individual heat radiation sheet10 and an area S₂ of the heat radiation sheet 11 integrally formed tocover the radiating region containing the controller 6 and the NANDs 5is S₁:S₂=0.0009:0.0035=1:3.9.

Coupling capacitance C of the parallel flat capacitor is represented bythe following Formula (1):

C=ε ₀ ×ε×S ₃ ÷d   (1)

In Formula (1), ε₀ represents a dielectric constant (F/m) in the vacuum,ε represents a relative dielectric constant of an object present betweenthe parallel flat plates, S₃ represents an area (m²) of the parallelflat plates, and d represents a distance (m) between the parallel flatplates.

In the SSD device according to this embodiment, an area of the printedcircuit board 3 smaller than the bottom housing 9 is the area of theparallel flat plates: S₃=0.063×0.0865=0.0054495 m². When the heatradiation sheets 10 or the heat radiation sheet 11 is present in a partbetween the parallel flat plates, the coupling capacitance of thecapacitor is a sum of coupling capacitance of a region where the heatradiation sheets 10 or the heat radiation sheet 11 is present andcoupling capacitance of a region where the heat radiation sheets 10 orthe heat radiation sheet 11 is not present.

It is assumed that a relative dielectric constant of the air isapproximated as 1. For simplification of explanation, it is assumed thata relative dielectric constant of electric components such as thecontroller 6 and the NANDs 5 is 1.

When the heat radiation sheets 10 or the heat radiation sheet 11 is notused, because only the air is present between the parallel flat plates,from Formula (1), coupling capacitance is8.85419×10⁻¹²×1×0.0054495÷0.0044=1.10×10⁻¹²F=11.0 pF.

When the individual heat radiation sheets 10 are used, an area of aregion where the heat radiation sheets 10 are present is 0.0009 m² andan area of a region where the heat radiation sheets 10 are not presentis 0.0045495 m². From Formula (1), coupling capacitance of the regionwhere the heat radiation sheets 10 are not present is8.85419×10⁻¹²×1×0.0045495÷0.0044=9.16×10⁻¹²F=9.16 pF.

On the other hand, coupling capacitance of the region where the heatradiation sheets 10 are present is series coupling capacitance ofcoupling capacitance of sections of the heat radiation sheets andcoupling capacitance of sections of the electronic components. Seriescoupling capacitance C_(c) of two capacitors C_(A) and C_(B) isrepresented by the following Formula (2):

1/C _(c)=(1/C _(A))+(1/C _(B))   (2)

From formula (1), coupling capacitance of sections of the heat radiationsheets 10 is 8.85419×10⁻¹²×5.8×0.0009÷0.003=5.9×10 ⁻¹²=5.69 pF. FromFormula (1), coupling capacitance of sections of the electroniccomponents is 8.85419×10⁻¹²×1×0.0009÷0.0014=1.5×10 ⁻¹¹F=15.4 pF.Therefore, from Formula (2), coupling capacitance of the entire areawhere the heat radiation sheets 10 are present is 4.16 pF. Therefore,coupling capacitance of the entire capacitors is 9.16 pF+4.16 pF−13.32pF.

When the heat radiation sheet 11 integrally formed to cover theradiating region containing the controller 6 and the NANDs 5 is used, anarea of a region where the heat radiation sheet 11 is present is 0.0035m² and an area of a region where the heat radiation sheet 11 is notpresent is 0.0019495 m². According to calculation same as thecalculation performed when the individual heat radiation sheet 10 isused, coupling capacitance of the region where the heat radiation sheet11 is not present is 3.92 pF and coupling capacitance of the regionwhere the heat radiation sheet 11 is present is 16.2 pF. Therefore,coupling capacitance of the entire capacitors is 20.1 pF.

As a result, the coupling capacitance can be reduced by about 44% byusing the individual heat radiation sheets 10 compared with the couplingcapacitance obtained when the heat radiation sheet 11 integrally formedto cover the radiating region containing the controller 6 and the NANDs5 is used.

An EMI characteristic of the SSD device including the individual heatradiation sheets 10 is shown in FIG. 14. An EMI characteristic of theSSD device including the heat radiation sheet 11 integrally formed tocover the radiating region containing the controller 6 and the NANDs 5is shown in FIG. 15. Measurement results by a test method specified inthe VCCI are shown in the figures. The computer is caused to operate ina state in which the SSD alone connected to the computer by an extensioncable is set on the outside of the computer (originally, the computer iscaused to operate in a state in which the SSD is incorporated in thecomputer as the apparatus on which the SSD is mounted). Intensity of anelectromagnetic wave (unnecessary radiation) entering an antenna set ina place 10 meters apart from the computer is measured. A conditionconforming to the VCCI standard is that the intensity is equal to orlower than 30 decibels in a band of 30 MHz to 230 MHz and is equal to orlower than 37 decibels in a band of 230 MHz to 1000 MHz. In the SSDdevice including the heat radiation sheet 11 integrally formed to coverthe radiating region containing the controller 6 and the NANDs 5, theintensity of the unnecessary radiation is over the standard value near700 MHz. On the other hand, in the SSD device including the individualheat radiation sheets 10, the intensity of the unnecessary radiation isreduced by about 16 decibels to be equal to or lower than the standardvalue near 700 MHz.

By using the individualized heat radiation sheets 10, the couplingcapacitance of the capacitor is reduced and the unnecessary radiationcaused by the bottom housing 9 functioning as the antenna is reduced. Torealize, with the heat radiation sheet 11 integrally formed to cover theradiating region containing the controller 6 and the NANDs 5, couplingcapacitance equivalent to that of the individual heat radiation sheets10, it is necessary to form the heat radiation sheet 11 with a materialhaving a relative dielectric constant of 1.586. However, in the presentsituation, it is difficult to form the heat radiation sheet 11 with sucha material. In other words, by using the individualized heat radiationsheets 10, it is possible to reduce the coupling capacitance to a levelthat cannot be realized when the heat radiation sheet 11 integrallyformed to cover the radiating region containing the controller 6 and theNANDs 5 is used and reduce the unnecessary radiation.

By individualizing the heat radiation sheet 10, it is also possible toreduce the weight of the SSD device. When the specific gravity of theheat radiation sheets 10 and 11 is set to 2.7, in the above example, adifference in an area is 0.0026 m² and the thickness of the sheet is0.003 meter, a weight difference is about 21 grams. In other words, byusing the individual heat radiation sheets 10, it is possible to reducethe weight by about 21 grams compared with the SSD device including theheat radiation sheet 11 integrally formed to cover the radiating regioncontaining the controller 6 and the NANDs 5.

In the example of the configuration explained above, the individual heatradiation sheets 10 are respectively arranged in the controller 6 andthe NANDs 5. However, as shown in FIG. 16, one heat radiation sheet canbe arranged in each of a plurality of cooling targets. In FIG. 16, eachof heat radiation sheets 10 a, 10 b, and 10 c covers three coolingtargets (one controller 6 and eight NANDs 5). By adopting such aconfiguration, it is possible to reduce manhour of work for sticking theheat radiation sheets and improve assembly workability. As the number ofcooling targets covered by one heat radiation sheet increases, theassembly workability is higher. On the other hand, the couplingcapacitance of the capacitor increases because the heat radiation sheetsare arranged in regions where cooling targets are not present. Theunnecessary radiation caused by the bottom housing 9 functioning as theantenna increases. In this way, the assembly workability in arrangingthe heat radiation sheets and the EMI characteristic of the SSD deviceare in a tradeoff relation. Therefore, it is advisable to select thenumber of cooling targets covered by one radiation sheet according torequired specifications.

Second Embodiment

FIG. 17 is a disassembled perspective view of the configuration of anSSD device according to a second embodiment. The configuration of theSSD device according to the second embodiment is the same as theconfiguration shown in FIG. 12. One heat radiation sheet 12 covers thecontroller 6 and the eight NANDs 5. The configuration of the lowersurface of the printed circuit board 3 of the semiconductor memorydevice 50 is also the same as that in the first embodiment. However, inthis embodiment, the relative dielectric constant of the heat radiationsheet 12 is 3.8, which is lower than that of the heat radiation sheets10 in the first embodiment.

As it is evident from Formula (1), the coupling capacitance of theparallel flat capacitor is proportional to the relative dielectricconstant of an object present between the parallel flat plates. It isassumed that dimensions of the heat radiation sheet 12 are the same asthe dimensions of the heat radiation sheet 11 explained in the firstembodiment and other conditions such as an area of the printed circuitboard 3 and a space between the bottom housing 9 and the printed circuitboard 3 are also the same. In this case, as the coupling capacitance ofthe parallel flat capacitor, according to Formulas (1) and (2), thecoupling capacitance of a region where the heat radiation sheet 12 isnot present is 3.92 pF and the coupling capacitance of a region wherethe heat radiation sheet 12 is present is 14.1 pF. Therefore, thecoupling capacitance of the entire capacitor is 18.0 pF. Therefore, byapplying a heat radiation sheet formed of a material having a lowrelative dielectric constant, it is possible to reduce the couplingcapacitance of the capacitor formed by the printed circuit board and thebottom housing and reduce the unnecessary radiation caused by the bottomhousing functioning as the antenna.

Third Embodiment

In an SSD device according to a third embodiment, as in the secondembodiment, one heat radiation sheet covers a controller and eightNANDs. A perspective view of a heat radiation sheet 13 according to thisembodiment is shown in FIG. 18. The heat radiation sheet 13 has astructure in which pieces 13 a corresponding to cooling targets and atabular section 13 b including the pieces 13 a on the surface thereofare integrally molded. By reducing a thickness dimension of the tabularsection 13 b, it is possible to suppress an increase in couplingcapacitance due to the presence of the tabular section 13 b between theprinted circuit board 3 and the bottom housing 9 compared with anincrease in coupling capacitance due to arranging a heat radiation sheetintegrally formed to cover the radiating region containing thecontroller 6 and the NANDs 5. Therefore, in this embodiment, thecoupling capacitance of a capacitor can be reduced compared with that inthe case of the heat radiation sheet is integrally formed to cover theradiating region containing the controller 6 and the NANDs 5. The heatradiation sheet 13 only has to be stuck once. Therefore, it is possibleto realize both an EMI characteristic and assembly workability.

Fourth Embodiment

FIGS. 20A and 20B are diagrams illustrating the printed circuit board 3of the SSD device according to the fourth embodiment. The SSD deviceaccording to the present embodiment has, like in the first embodiment,the connector 4, the NANDs 5, the controller 6, and the SDRAM 7 mountedon the printed circuit board 3. Also, the individually-segmentedradiation sheets 10 are arranged on the controller 6 and the NANDs 5. Inthe present embodiment, however, the radiation sheets 10 are arranged onnot all of the controller 6 and the NANDs 5, but a portion thereof. FIG.20A illustrates a configuration in which six sheets of the radiationsheet 10 are arranged and FIG. 20B illustrates a configuration in whichfive sheets of the radiation sheet 10 are arranged. In bothconfigurations, the radiation sheet 10 is not arranged on the NANDs 5positioned at corners of a cluster in a substantial rectangular shape ofthe SDRAM 7, the controller 6, and the NANDs 5 arranged in a rectangularcluster.

The printed circuit board 3 has a temperature sensor IC 60 having afunction to output temperature measurement results mounted thereon.

FIG. 21A is a diagram illustrating temperature measurement results(Celsius temperature) when an SSD device according to the presentembodiment is caused to continuously write data at the transfer rate of192 MB/sec at room temperature in an atmosphere of no wind. FIG. 21B isa diagram illustrating temperature measurement locations on each devicemounted on the printed circuit board 3. No. 2 to No. 6 measurementlocations in FIG. 21A are locations indicated by arrows of (2) to (6) inFIG. 21B. No. 1 measurement location in FIG. 21A is an atmosphere inwhich the SSD device is installed and No. 7 measurement location is asurface of the housing on the side of the controller 6. Temperaturemeasurement results at each location when, as illustrated in FIG. 12,the SSD device is caused to continuously write data at 192 MB/sec bycovering a substantially entire surface of the printed circuit board 3with one radiation sheet, temperature measurement results at eachlocation when the SSD device is caused to continuously write data at 189MB/sec with no radiation sheet, and temperature measurement results ateach location when the SSD device is caused to continuously write dataat 192 MB/sec by arranging the radiation sheet 10 on all of thecontroller 6 and the NANDs 5 are illustrated for comparison. Athermocouple is used for temperature measurement. Further, measurementresults by the temperature sensor IC 60 are also illustrated togetherwith temperature measurement results at each location. Regarding eachconfiguration in which a radiation sheet is provided, measurementresults by the thermocouple on each device mounted on the printedcircuit board 3 and measurement results by the temperature sensor IC 60are values close to each other, which illustrates that measurementresults by the temperature sensor IC 60 are reliable.

The temperature of the controller 6 is lower when the number of theradiation sheets 10 is six (6 pcs) than when the number of the radiationsheets 10 is five (5 pcs). The temperature of the controller 6 when thenumber of the radiation sheets 10 is nine (9 pcs) is approximately thesame as the temperature of the controller 6 when the number of theradiation sheets 10 is six (6 pcs). The temperature of the NAND 5 isapproximately the same when the number of the radiation sheets 10 isfive and the number of the radiation sheets 10 is six. The temperatureof the NAND 5 when the number of the radiation sheets 10 is nine isfurther lower than the temperature of the NAND 5 when the number of theradiation sheets 10 is six.

It is assumed here that the temperature of each device should be 85° C.or less when the temperature of the housing is set to 70° C. and anincrease in temperature at each location will be calculated based ontemperature measurement results illustrated in FIG. 21A. (Calculatetemperature differences from the temperature of the housing) FIG. 22 isa diagram illustrating temperature differences between each devicemounted on the printed circuit board 3 and the housing and maximumtemperatures of devices when the housing temperature is assumed to be70° C. In all configurations in which the number of the radiation sheets10 is five, six, and nine, the maximum value of temperature differencebetween the housing and each device (the SDRAM 7, the controller 6, andthe NAND 5) is less than 15° C. and thus, if the temperature of thehousing is set to 70° C., the temperature of all devices is less than85° C. so that it is possible to verify that requirements concerning thedevice temperature can be met.

The configuration in which the number of the radiation sheets 10 is fiveis lighter and costs less, but the temperature difference from thetemperature of the housing is large. Though the configuration in whichthe number of the radiation sheets 10 is six is heavier than theconfiguration in which the number of the radiation sheets 10 is five,the temperature difference from the temperature of the housing becomessmaller. Thus, the number of the radiation sheets 10 can be decided asappropriate by considering the weight, cost, and the magnitude oftemperature difference from the temperature of the housing within therange in which a product meets requirements concerning the devicetemperature. Therefore, heat dissipation performance can be ensuredwhile reducing the weight and material costs by arranging the radiationsheets 10 on a portion of the controller 6 and the NANDs 5.

In the configuration explained as the example in the embodiments, thecontroller 6 and the NANDs 5 are mounted on the lower surface of theprinted circuit board 3 and the heat radiation sheets 10, the heatradiation sheet 12, or the heat radiation sheet 13 is arranged betweenthe printed circuit board 3 and the bottom housing 9. However, it goeswithout saying that the same effect can be obtained even when thecontroller 6 and the NANDs 5 are mounted on the upper surface of theprinted circuit board 3 and a heat radiation sheet(s) is arrangedbetween the printed circuit board 3 and the top cover 1.

In the configuration explained as the example in the embodiments, theNANDs 5 are mounted on only the lower surface of the printed circuitboard 2. However, it is also possible to adopt a configuration in whichthe printed circuit board 3 mounted with the NANDs 5 on both thesurfaces is used. FIG. 19 is a disassembled perspective view of theconfiguration of an SSD device including the printed circuit board 3mounted with the NANDs 5 on both the surfaces. The configuration of thelower surface of the printed circuit board 3 of the semiconductor memorydevice 50 is the same as that shown in FIG. 1B. When the printed circuitboard 3 mounted with the NANDs 5 on both the surfaces is used,individual heat radiation sheets 15 (second heat radiation members) sameas the heat radiation sheets 10 in the first embodiment are arrangedbetween the NANDs 5 as second nonvolatile semiconductor memories on theupper surface side of the printed circuit board 3 and the top cover 1.This makes it possible the coupling capacitance of a parallel flatcapacitor formed by the printed circuit board 3 and the top cover 1 issmaller than the coupling capacitance when an integrally formed objecthaving a relative dielectric constant of 5.8 is arranged between thecapacitor to cover a radiating region (second radiating region)containing the second nonvolatile semiconductor memories on the uppersurface side of the printed circuit board 3 and reduce unnecessaryradiation caused by the top cover 1 functioning as an antenna. It goeswithout saying that the same effect can be obtained even if the heatradiation sheets 15 are the same as those in the second, third andfourth embodiments. It goes without saying that, like the first heatradiation member, the second heat radiation member can be a gel member.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the sprit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1. A semiconductor memory device comprising: a circuit board including a circuit pattern; a nonvolatile semiconductor memory; and a connector that is capable of being coupled with a host apparatus, wherein the circuit board includes a first surface, a second surface located opposite to the first surface, a first end having the connector, a second end in which a cutout is formed, and a corner intersected with the first end and the second end, the nonvolatile semiconductor memory is mounted on the first surface, the semiconductor memory device is configured to be capable of being housed in a housing, the housing including a first side and a second side, the second side being adjacent to the first side, the housing including a coupling portion, the coupling portion being fixed to the host apparatus and located on the second side, the second side facing the second end, the connector is configured to pass through the first side of the housing, the semiconductor memory device is configured to be capable of being housed in the housing in a position in which a center axis of the first surface along a direction in which the connector connects to the host apparatus is shifted toward the second side with respect to a center axis of the housing along the direction in which the connector connects to the host apparatus, and the cutout is configured to be capable of holding, inside, a part of the coupling portion.
 2. The semiconductor memory device according to claim 1, wherein the coupling portion includes a screw and a screw hole through which the screw is inserted, the screw hole being formed through the second side.
 3. The semiconductor memory device according to claim 2, wherein the screw projects into the housing, wherein the cutout is configured to avoid interference between the projecting screw and the circuit board.
 4. The semiconductor memory device according to claim 3, wherein a shape of the connector and a position of the connector with respect to the housing conform to a Serial Advanced Technology Attachment standard.
 5. The semiconductor memory device according to claim 4, wherein the housing is a 2.5-inch-type housing.
 6. The semiconductor memory device according to claim 1, wherein a predetermined space is formed between the cutout and the circuit pattern.
 7. The semiconductor memory device according to claim 1, wherein the circuit board has an eight-layer structure.
 8. The semiconductor memory device according to claim 1, wherein the circuit board has a substantially rectangular shape in plane view, wherein the first end is an end of longer dimension of the circuit board, wherein the second end is an end of shorter dimension of the circuit board.
 9. The semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory.
 10. A box-type semiconductor memory device comprising: a semiconductor memory including: a circuit board including a circuit pattern; a nonvolatile semiconductor memory; and a connector that is capable of being coupled with a host apparatus; and a housing that houses the semiconductor memory, wherein the housing includes: a first side; and a second side, the second side being adjacent to the first side and on the second side, a coupling portion being fixed to the host apparatus, the circuit board includes a first surface, a second surface located opposite to the first surface, a first end having the connector, a second end in which a cutout is formed, and a corner intersected with the first end and the second end, the nonvolatile semiconductor memory is mounted on the first surface, the connector is configured to pass through the first side of the housing, the housing is configured to house the semiconductor memory in a position in which a center axis of the first surface along a direction in which the connector connects to the host apparatus is shifted toward the second side with respect to a center axis of the housing along the direction in which the connector connects to the host apparatus, and the cutout is configured to hold inside, a part of the coupling portion.
 11. The box-type semiconductor memory device according to claim 10, wherein the coupling portion includes a screw and a screw hole through which the screw is inserted, the screw hole being formed through the second side.
 12. The box-type semiconductor memory device according to claim 11, wherein the screw projects into the housing, and the cutout is configured to avoid interference between the projecting screw and the circuit board.
 13. The box-type semiconductor memory device according to claim 12, wherein a shape of the connector and a position of the connector with respect to the housing conform to a Serial Advanced Technology Attachment standard.
 14. The box-type semiconductor memory device according to claim 13, wherein the housing is a 2.5-inch-type housing.
 15. The box-type semiconductor memory device according to claim 10, wherein a predetermined space is formed between the cutout and the circuit pattern.
 16. The box-type semiconductor memory device according to claim 10, wherein the circuit board has an eight-layer structure.
 17. The box-type semiconductor memory device according to claim 10, wherein the circuit board has a substantially rectangular shape in plane view, wherein the first end is an end of longer dimension of the circuit board, wherein the second end is an end of shorter dimension of the circuit board.
 18. The box-type semiconductor memory device according to claim 10, wherein the nonvolatile semiconductor memory is a NAND flash memory.
 19. A semiconductor memory device comprising: a nonvolatile semiconductor memory; and a circuit board including a first end having a connector and a second end in which a cutout portion is formed, wherein, in a state in which the circuit board is mounted in a housing, the cutout portion is configured to be capable of holding, inside, at least a part of a fixing portion, the fixing portion being formed through a side of the housing, the fixing portion being fixed to an external host apparatus.
 20. A memory system comprising: a housing in which, through a side, a fixing portion being fixed to an external host apparatus is formed; a nonvolatile semiconductor memory; a connector that is capable of being coupled with the external host apparatus; and a circuit board including a first end having the connector and a second end in which a cutout is formed, the cutout holding, inside, at least a part of the fixing portion. 